| Secda: Efficient hardware/software co-design of fpga-based dnn accelerators for edge inference J Haris, P Gibson, J Cano, NB Agostini, D Kaeli 2021 IEEE 33rd International Symposium on Computer Architecture and High …, 2021 | 15 | 2021 |
| SECDA-TFLite: A toolkit for efficient development of FPGA-based DNN accelerators for edge inference J Haris, P Gibson, J Cano, NB Agostini, D Kaeli Journal of Parallel and Distributed Computing 173, 140-151, 2023 | 4 | 2023 |
| AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators NB Agostini, J Haris, P Gibson, M Jayaweera, N Rubin, A Tumeo, ... 2024 IEEE/ACM International Symposium on Code Generation and Optimization …, 2024 | 1 | 2024 |
| Hardware Acceleration of Deep Neural Networks on Edge Devices with FPGAs J Haris, J Cano Reyes | 1 | 2020 |
| Data Transfer Optimizations for Host-CPU and Accelerators in AXI4MLIR J Haris, NB Agostini, A Tumeo, D Kaeli, J Cano arXiv preprint arXiv:2402.19184, 2024 | | 2024 |
| AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators N Bohm Agostini, J Haris, P Gibson, M Jayaweera, N Rubin, A Tumeo, ... arXiv e-prints, arXiv: 2312.14821, 2023 | | 2023 |
| Hardware/Software Co-Design of Edge DNN Accelerators with TFLite J Haris, P Gibson, J Cano, NB Agostini, D Kaeli | | 2022 |
