The exanest project: Interconnects, storage, and packaging for exascale systems M Katevenis, N Chrysos, M Marazakis, I Mavroidis, F Chaix, N Kallimanis, ... 2016 Euromicro Conference on Digital System Design (DSD), 60-67, 2016 | 61 | 2016 |
APEnet+: a 3D Torus network optimized for GPU-based HPC Systems R Ammendola, A Biagioni, O Frezza, FL Cicero, A Lonardo, PS Paolucci, ... Journal of Physics: Conference Series 396 (4), 042059, 2012 | 59 | 2012 |
Gpu peer-to-peer techniques applied to a cluster interconnect R Ammendola, M Bernaschi, A Biagioni, M Bisson, M Fatica, O Frezza, ... 2013 IEEE International Symposium on Parallel & Distributed Processing …, 2013 | 45 | 2013 |
APEnet+: high bandwidth 3D torus direct network for petaflops scale commodity clusters R Ammendola, A Biagioni, O Frezza, FL Cicero, A Lonardo, PS Paolucci, ... Journal of Physics: Conference Series 331 (5), 052029, 2011 | 37 | 2011 |
HIKE, High Intensity Kaon Experiments at the CERN SPS: Letter of Intent HIKE Collaboration, EC Gil arXiv preprint arXiv:2211.16586, 2022 | 31* | 2022 |
NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs R Ammendola, A Biagioni, O Frezza, G Lamanna, A Lonardo, FL Cicero, ... Journal of Instrumentation 9 (02), C02023, 2014 | 29 | 2014 |
The next generation of Exascale-class systems: The ExaNeSt project R Ammendola, A Biagioni, P Cretaro, O Frezza, FL Cicero, A Lonardo, ... 2017 Euromicro Conference on Digital System Design (DSD), 510-515, 2017 | 27 | 2017 |
Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development M Katevenis, R Ammendola, A Biagioni, P Cretaro, O Frezza, FL Cicero, ... Microprocessors and Microsystems 61, 58-71, 2018 | 26 | 2018 |
APEnet+ 34 Gbps data transmission system and custom transmission logic R Ammendola, A Biagioni, O Frezza, A Lonardo, FL Cicero, PS Paolucci, ... Journal of Instrumentation 8 (12), C12022, 2013 | 25 | 2013 |
QUonG: A GPU-based HPC system dedicated to LQCD computing R Ammendola, A Biagioni, O Frezza, FL Cicero, A Lonardo, PS Paolucci, ... 2011 Symposium on Application Accelerators in High-Performance Computing …, 2011 | 23 | 2011 |
Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms PS Paolucci, A Biagioni, LG Murillo, F Rousseau, L Schor, L Tosoratto, ... Journal of Systems Architecture 69, 29-53, 2016 | 22 | 2016 |
Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities R Ammendola, A Biagioni, O Frezza, FL Cicero, A Lonardo, PS Paolucci, ... 2013 International Conference on Field-Programmable Technology (FPT), 58-65, 2013 | 21 | 2013 |
NaNet-10: a 10GbE network interface card for the GPU-based low-level trigger of the NA62 RICH detector. R Ammendola, A Biagioni, M Fiorini, O Frezza, A Lonardo, G Lamanna, ... Journal of Instrumentation 11 (03), C03030, 2016 | 20 | 2016 |
Power, energy and speed of embedded and server multi-cores applied to distributed simulation of spiking neural networks: ARM in NVIDIA Tegra vs Intel Xeon quad-cores PS Paolucci, R Ammendola, A Biagioni, O Frezza, FL Cicero, A Lonardo, ... arXiv preprint arXiv:1505.03015, 2015 | 20 | 2015 |
Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale … PS Paolucci, R Ammendola, A Biagioni, O Frezza, FL Cicero, A Lonardo, ... arXiv preprint arXiv:1310.8478, 2013 | 19 | 2013 |
NaNet: a configurable NIC bridging the gap between HPC and real-time HEP GPU computing A Lonardo, F Ameli, R Ammendola, A Biagioni, AC Ramusino, M Fiorini, ... Journal of Instrumentation 10 (04), C04011, 2015 | 18 | 2015 |
Power-efficient computing: experiences from the COSA project D Cesini, E Corni, A Falabella, A Ferraro, L Morganti, E Calore, ... Scientific Programming 2017, 2017 | 15 | 2017 |
Introduction to the Tiled HW Architecture of SHAPES PS Paolucci, F Lo Cicero, A Lonardo, M Perra, D Rossetti, C Sidore, ... Proceedings of IEEE DATE 2007, 79-82, 2007 | 15 | 2007 |
A hierarchical watchdog mechanism for systemic fault awareness on distributed systems R Ammendola, A Biagioni, O Frezza, FL Cicero, A Lonardo, PS Paolucci, ... Future Generation Computer Systems 53, 90-99, 2015 | 11 | 2015 |
NaNet: a low-latency NIC enabling GPU-based, real-time low level trigger systems R Ammendola, A Biagioni, R Fantechi, O Frezza, G Lamanna, FL Cicero, ... Journal of Physics: Conference Series 513 (1), 012018, 2014 | 11 | 2014 |