| Universal asynchronous receiver and transmitter (uart) U Nanda, SK Pattnaik 2016 3rd international conference on advanced computing and communication …, 2016 | 44 | 2016 |
| A new transmission gate cascode current mirror charge pump for fast locking low noise PLL U Nanda, DP Acharya, SK Patra Circuits, Systems, and Signal Processing 33 (9), 2709-2718, 2014 | 22 | 2014 |
| A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate D Nayak, DP Acharya, PK Rout, U Nanda Microelectronics Journal 73, 43-51, 2018 | 19 | 2018 |
| Design of LC VCO for optimal figure of merit performance using CMODE PK Rout, UK Nanda, DP Acharya, G Panda 2012 1st International Conference on Recent Advances in Information …, 2012 | 17 | 2012 |
| Design and implementation of different types of full adders in ALU and leakage minimization SK Pattnaik, U Nanda, D Nayak, SR Mohapatra, AB Nayak, A Mallick 2017 International Conference on Trends in Electronics and Informatics (ICEI …, 2017 | 14 | 2017 |
| Design of an efficient phase frequency detector to reduce blind zone in a PLL U Nanda, DP Acharya, SK Patra Microsystem Technologies 23 (3), 533-539, 2017 | 14 | 2017 |
| A novel charge recycle read write assist technique for energy efficient and fast 20 nm 8T-SRAM array D Nayak, DP Acharya, PK Rout, U Nanda Solid-State Electronics 148, 43-50, 2018 | 12 | 2018 |
| Design of a low noise PLL for GSM application U Nanda, DP Acharya, SK Patra 2013 International conference on Circuits, Controls and Communications …, 2013 | 12 | 2013 |
| Optimization of an application specific instruction set processor using application description language VR Dodani, N Kumar, U Nanda, K Mahapatra 2010 5th International Conference on Industrial and Information Systems, 325-328, 2010 | 11 | 2010 |
| Nanowire Array-based MOSFET for future CMOS technology to attain the ultimate scaling limit K Bhol, U Nanda Silicon 14 (3), 1169-1177, 2022 | 10 | 2022 |
| Performance analysis of gate-stack dual-material DG MOSFET using work-function modulation technique for lower technology nodes SK Das, U Nanda, SM Biswal, CK Pandey, LI Giri Silicon 14 (6), 2965-2973, 2022 | 9 | 2022 |
| Performance analysis of ferroelectric gaa mosfet with metal grain work function variability B Jena, K Bhol, U Nanda, S Tayal, SR Routray Silicon 14 (6), 3005-3012, 2022 | 9 | 2022 |
| Smart power theft detection system NK Mucheli, U Nanda, D Nayak, PK Rout, SK Swain, SK Das, SM Biswal 2019 Devices for Integrated Circuit (DevIC), 302-305, 2019 | 9 | 2019 |
| Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios U Nanda, DP Acharya Microelectronics Journal 64, 92-98, 2017 | 9 | 2017 |
| RF and linearity parameter analysis of junction-less gate all around (JLGAA) MOSFETs and their dependence on gate work function P Raut, U Nanda Silicon, 1-9, 2021 | 7 | 2021 |
| Effect of high-K spacer on the performance of non-uniformly doped DG-MOSFET SK Swain, SK Das, SM Biswal, S Adak, U Nanda, AA Sahoo, D Navak, ... 2019 Devices for Integrated Circuit (DevIC), 510-514, 2019 | 7 | 2019 |
| Advances in analog integrated circuit optimization: a survey PK Rout, DP Acharya, U Nanda Handbook of research on applied optimization methodologies in manufacturing …, 2018 | 7 | 2018 |
| Design and implementaton of SRAM macro unit SN Panda, S Padhi, V Phanindra, U Nanda, SK Pattnaik, D Nayak 2017 International Conference on Trends in Electronics and Informatics (ICEI …, 2017 | 6 | 2017 |
| Low noise and fast locking phase locked loop using a variable delay element in the phase frequency detector U Nanda, DP Acharya, SK Patra Journal of Low Power Electronics 10 (1), 53-57, 2014 | 6 | 2014 |
| Study on analog/RF and linearity performance of staggered heterojunction gate stack tunnel FET SM Biswal, SK Das, S Misra, U Nanda, B Jena ECS Journal of Solid State Science and Technology 10 (7), 073001, 2021 | 5 | 2021 |
Debasish NayakSilicon Institute of Technology, BhubaneswarVerified email at silicon.ac.in
