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Scott Springer
Scott Springer
IBM & Globalfoundries
Verified email at ieee.org
Title
Cited by
Cited by
Year
Record RF performance of 45-nm SOI CMOS technology
S Lee, B Jagannathan, S Narasimha, A Chou, N Zamdmer, J Johnson, ...
2007 IEEE International Electron Devices Meeting, 255-258, 2007
2352007
Modeling of variation in submicrometer CMOS ULSI technologies
SK Springer, S Lee, N Lu, EJ Nowak, JO Plouchart, JS Watts, RQ Williams, ...
IEEE Transactions on Electron Devices 53 (9), 2168-2178, 2006
992006
Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices
S Lee, R Wachnik, P Hyde, L Wagner, J Johnson, A Chou, A Kumar, ...
2013 Symposium on VLSI Technology, T248-T249, 2013
412013
SOI CMOS Technology with 360GHz f T NFET, 260GHz f T PFET, and Record Circuit Performance for Millimeter-Wave Digital and Analog System-on-Chip Applications
S Lee, J Kim, D Kim, B Jagannathan, C Cho, J Johnson, B Dufrene, ...
2007 IEEE Symposium on VLSI Technology, 54-55, 2007
282007
Experimental Study of Gate-First FinFET Threshold-Voltage Mismatch
Q Zhang, C Wang, H Wang, C Schnabel, DG Park, SK Springer, ...
Electron Devices, IEEE Transactions on 61 (2), 643-646, 2014
262014
Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications
S Lee, J Johnson, B Greene, A Chou, K Zhao, M Chowdhury, J Sim, ...
2012 Symposium on VLSI Technology (VLSIT), 135-136, 2012
202012
Method for treating parasitic resistance, capacitance, and inductance in the design flow of integrated circuit extraction, simulations, and analyses
N Lu, SK Springer
US Patent App. 11/458,240, 2008
192008
Gate stack resistance and limits to CMOS logic performance
RA Wachnik, S Lee, LH Pan, H Li, N Lu, J Wang, C Bernicot, R Bingert, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (8), 2318-2325, 2014
162014
High-performance FET device layout
J Kim, S Lee, JO Plouchart, SK Springer
US Patent 7,791,160, 2010
142010
High-performance FET device layout
J Kim, S Lee, JO Plouchart, SK Springer
US Patent 7,689,946, 2010
122010
Cmos varactor
S Lee, SK Springer
US Patent App. 11/847,378, 2009
112009
Temperature-compliant integrated circuits
JM Johnson, S Lee, L Luo, SK Springer
US Patent 9,928,335, 2018
72018
SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing
J Deng, A Rahman, R Thoma, PW Schneider, J Johnson, H Trombley, ...
IEEE, 2015
72015
A half-micron manufacturable high performance CMOS technology applicable for multiple power supply applications
A Bhattacharyya, R Mann, E Nowak, R Piro, J Springer, S Springer, ...
International Symposium on VLSI Technology, Systems and Applications,, 321-326, 1989
71989
Integrated circuits with Peltier cooling provided by back-end wiring
SO Koswatta, S Lee, L Luo, SK Springer, RA Wachnik
US Patent 10,103,083, 2018
4*2018
System, method and program storage device for developing condensed netlists representative of groups of active devices in an integrated circuit and for modeling the performance …
Y Deng, PA Hyde, JM Johnson, TG McKenzie, SK Springer, RQ Williams
US Patent 8,392,867, 2013
42013
Elements of statistical SPICE models
N Lu, J Watts, SK Springer
Proceedings of theNSTI Nanotechnology Conference and Expo (NSTI-Nanotech’09 …, 2009
42009
Method, system and program storage device for generating accurate performance targets for active semiconductor devices during new technology node development
JM Johnson, SK Springer, R Thoma, JS Watts
US Patent 8,453,101, 2013
32013
Integrated circuits with Peltier cooling provided by back-end wiring
SO Koswatta, S Lee, L Luo, SK Springer, RA Wachnik
US Patent 10,103,083, 2018
22018
Modeling of Gate Leakage, Floating Body Effect, and History Effect in 32nm HKMG PD-SOI CMOS
Y Deng, R Rupani, J Johnson, S Springer
Proc. of NSTI-Nanotech, 2010
22010
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