| Charge Trap Transistor (CTT): An Embedded Fully Logic-Compatible Multiple-Time Programmable Non-Volatile Memory Element for High- -Metal-Gate CMOS … F Khan, E Cartier, JCS Woo, SS Iyer IEEE Electron Device Letters 38 (1), 44-47, 2017 | 56 | 2017 |
| The Impact of Self-Heating on Charge Trapping in High- -Metal-Gate nFETs F Khan, E Cartier, C Kothandaraman, JC Scott, JCS Woo, SS Iyer IEEE Electron Device Letters 37 (1), 88-91, 2016 | 44 | 2016 |
| 80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity J Viraraghavan, D Leu, B Jayaraman, A Cestero, R Kilker, M Yin, J Golz, ... 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 27 | 2016 |
| Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications C Kothandaraman, X Chen, D Moy, D Lea, S Rosenblatt, F Khan, D Leu, ... 2015 IEEE International Reliability Physics Symposium, MY. 2.1-MY. 2.4, 2015 | 24 | 2015 |
| Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies F Khan, MS Han, D Moy, R Katz, L Jiang, E Banghart, N Robson, ... IEEE Electron Device Letters 40 (7), 1100-1103, 2019 | 19 | 2019 |
| 80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity B Jayaraman, D Leu, J Viraraghavan, A Cestero, M Yin, J Golz, ... IEEE Journal of Solid-State Circuits 53 (3), 949-960, 2018 | 19 | 2018 |
| Turning Logic Transistors into Secure, Multi-Time Programmable, Embedded Non-Volatile Memory Elements for 14 nm FINFET Technologies and Beyond F Khan, D Moy, D Anand, EH Schroeder, R Katz, L Jiang, E Banghart, ... 2019 Symposium on VLSI Technology, T116-T117, 2019 | 14 | 2019 |
| 14-nm FinFET 1.5 Mb Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Differential Current Sensing E Hunt-Schroeder, D Anand, J Fifield, M Roberge, D Pontius, M Jacunski, ... IEEE Solid-State Circuits Letters 1 (12), 233-236, 2018 | 9 | 2018 |
| Charge Trap Transistors (CTT): Turning Logic Transistors into Embedded Non-Volatile Memory for Advanced High-k/Metal Gate CMOS Technologies F Khan University of California, Los Angeles (UCLA), 2020 | 3 | 2020 |
| Program and erase memory structures F Khan, NW Robson, T Kirihata, D Moy, DL Anand US Patent 10,685,705, 2020 | 1 | 2020 |
| Charge trap memory devices F Khan, D Moy, NW Robson, R Katz, DL Anand, T Kirihata US Patent 11,367,734, 2022 | | 2022 |
| Charge Trap Transistors (CTT): A Process/Mask-Free Secure Embedded Non-Volatile Memory for 14 nm FinFET Technologies and Beyond {Invited Talk} F Khan 2020 Microelectronics Reliability and Qualification Workshop (MRQW), 2020 | | 2020 |
| Design and Development Challenges of Charge Trap Transistor Memories SV E. Hunt-Schroeder, D. Anand, D. Pontius, M. Roberge, D. Moy, E. Banghart ... Government Microcircuit Applications & Critical Technology (GOMACTech …, 2020 | | 2020 |
| Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET F Khan | | 2019 |
| A Multi-Time Programmable Memory Technology in a Native 14nm FINFET Process using Charge Trap Transistors (CTTs) F Khan, E Hunt-Schroeder, D Moy, D Anand, R Katz, D Leu, J Fifield, ... Government Microcircuit Applications & Critical Technology (GOMACTech …, 2019 | | 2019 |
| Charge Trap Transistors (CTT): Turning Logic Transistors into Embedded Non-Volatile F Khan | | 2019 |
| Charge Trap Transistors (CTT): Turning Logic Transistors into Embedded Non-Volatile Memory for Advanced High-k/Metal Gate CMOS Technologies F Khan UCLA, 2019 | | 2019 |
| Annealing effects on ZnO TFTs grown by MOCVD CJ Ku, PI Rayes, CC Kuo, F Khan Abstract Book of the 6th International Workshop on ZnO and Related Materials, 2010 | | 2010 |
| Endurance characterization and improvement of floating gate semiconductor memory devices F Khan | | 2009 |
