| CRUISE: Cache replacement and utility-aware scheduling A Jaleel, HH Najaf-Abadi, S Subramaniam, SC Steely, J Emer Proceedings of the seventeenth international conference on Architectural …, 2012 | 118 | 2012 |
| Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features MC Adler, C Chou, NC Crago, K Fleming, KD Glossop, A Jaleel, ... US Patent 10,387,319, 2019 | 43 | 2019 |
| Processors, methods, and systems for a configurable spatial accelerator with transactional and replay features K Fleming, KD Glossop, SC Steely Jr, SS Sury US Patent 10,445,234, 2019 | 38 | 2019 |
| High performance parallel stochastic gradient descent in shared memory S Sallinen, N Satish, M Smelyanskiy, SS Sury, C Ré 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2016 | 38 | 2016 |
| Software-transparent hardware predictor for core-to-core data transfer optimization R Wang, J Nuzman, SS Sury, AJ Herdrich, NN Venkatesan, A Vasudevan, ... US Patent 10,635,590, 2020 | 35 | 2020 |
| Instruction prefetching using cache line history S Subramaniam, A Jaleel, SC Steely Jr US Patent 8,533,422, 2013 | 32 | 2013 |
| PEEP: Exploiting predictability of memory dependences in SMT processors S Subramaniam, M Prvulovic, GH Loh 2008 IEEE 14th International Symposium on High Performance Computer …, 2008 | 23 | 2008 |
| Hardware apparatuses and methods to control cache line coherency SC Steely Jr, SS Sury, WC Hasenplaugh US Patent 9,934,146, 2018 | 18 | 2018 |
| Hardware apparatuses and methods to control cache line coherence S Sury, S Steely Jr, W Hasenplaugh, J Emer, D Webb US Patent 9,740,617, 2017 | 17 | 2017 |
| Instructions for remote atomic operations DN Jayasimha, J Svennebring, SS Sury, CJ Hughes, JS Park, L Xiang US Patent App. 15/638,120, 2019 | 11 | 2019 |
| Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers WC Hasenplaugh, CJ Newburn, SC Steely Jr, SS Sury US Patent 10,379,855, 2019 | 8 | 2019 |
| Address range priority mechanism S Steely Jr, S Subramaniam, WC Hasenplaugh US Patent 9,477,610, 2016 | 8 | 2016 |
| Spatial and temporal merging of remote atomic operations CJ Hughes, J Nuzman, J Svennebring, DN Jayasimha, SS Sury, ... US Patent 10,572,260, 2020 | 6 | 2020 |
| Method and apparatus for adaptively selecting data transfer processes for single-producer-single-consumer and widely shared cache lines SS Sury, RG Blankenship, SC Steely Jr, YC Liu US Patent App. 15/721,121, 2019 | 6 | 2019 |
| Planning your sql-on-hadoop deployment using a low-cost simulation-based approach J Liu, B Bian, SS Sury 2016 28th International Symposium on Computer Architecture and High …, 2016 | 6 | 2016 |
| Short circuit of probes in a chain SC Steely Jr, S Subramaniam, WC Hasenplaugh, JS Emer US Patent 9,201,792, 2015 | 6 | 2015 |
| High bandwidth full-block write commands SC Steely Jr, WC Hasenplaugh, JS Emer, S Subramaniam US Patent 10,102,124, 2018 | 5 | 2018 |
| Using in-flight chains to build a scalable cache coherence protocol S Subramaniam, SC Steely, W Hasenplaugh, A Jaleel, C Beckmann, ... ACM Transactions on Architecture and Code Optimization (TACO) 10 (4), 1-24, 2013 | 5 | 2013 |
| Remote atomic operations in multi-socket systems DN Jayasimha, SS Sury, CJ Hughes, J Svennebring, YC Liu, ... US Patent 10,296,459, 2019 | 4 | 2019 |
| Apparatus and method for multi-level cache request tracking RG Blankenship, SS Sury US Patent 10,310,978, 2019 | 3 | 2019 |
