| Field tolerant dynamic intrinsic chip ID using 32 nm high-k/metal gate SOI embedded DRAM S Rosenblatt, D Fainstein, A Cestero, J Safran, N Robson, T Kirihata, ... IEEE journal of solid-state circuits 48 (4), 940-947, 2013 | 60 | 2013 |
| 3D stackable 32nm High-K/Metal Gate SOI embedded DRAM prototype J Golz, J Safran, B He, D Leu, M Yin, T Weaver, A Vehabovic, Y Sun, ... VLSI Circuits (VLSIC), 2011 Symposium on, 228-229, 2011 | 33 | 2011 |
| Retention based intrinsic fingerprint identification featuring a fuzzy algorithm and a dynamic key DJ Fainstein, A Cestero, SS Iyer, T Kirihata, NW Robson, S Rosenblatt US Patent 8,590,010, 2013 | 32 | 2013 |
| Chip authentication using multi-domain intrinsic identifiers S Rosenblatt, DJ Fainstein, T Kirihata US Patent 9,202,040, 2015 | 21 | 2015 |
| Dynamic Intrinsic Chip ID Using 32nm High-K/Metal Gate SOI Embedded DRAM D Fainstein, S Rosenblatt, A Cestero, N Robson, T Kirihata, SS Iyer | 15* | |
| Undiscoverable physical chip identification DJ Fainstein, C Kothandaraman US Patent 8,950,008, 2015 | 13 | 2015 |
| Physical design symmetry and integrated circuits enabling three dimentional (3D) yield optimization for wafer to wafer stacking JM Safran, DJ Fainstein, GW Maier, Y Song, NW Robson US Patent 9,029,234, 2015 | 10 | 2015 |
| Undiscoverable physical chip identification DJ Fainstein, C Kothandaraman US Patent 9,298,950, 2016 | 2 | 2016 |
| Circuits for self-reconfiguration or intrinsic functional changes of chips before vs. after stacking NW Robson, DJ Fainstein US Patent 9,194,912, 2015 | | 2015 |
| DRAM and Memory Interfaces J Golz, J Safran, B He, D Leu, M Yin, T Weaver, A Vehabovic, Y Sun, ... | | |
