| Crono: A benchmark suite for multithreaded graph algorithms executing on futuristic multicores M Ahmad, F Hijaz, Q Shi, O Khan 2015 IEEE International Symposium on Workload Characterization, 44-55, 2015 | 133 | 2015 |
| Survey of fall detection and daily activity monitoring techniques F Hijaz, N Afzal, T Ahmad, O Hasan 2010 International Conference on Information and Emerging Technologies, 1-6, 2010 | 77 | 2010 |
| Accelerating graph and machine learning workloads using a shared memory multicore architecture with auxiliary support for in-hardware explicit messaging H Dogan, F Hijaz, M Ahmad, B Kahne, P Wilson, O Khan 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2017 | 25 | 2017 |
| A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages F Hijaz, Q Shi, O Khan 2013 IEEE 31st International Conference on Computer Design (ICCD), 85-92, 2013 | 18 | 2013 |
| Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication F Hijaz, B Kahne, P Wilson, O Khan 2015 IEEE International Conference on Networking, Architecture and Storage …, 2015 | 13 | 2015 |
| ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores O Khan, H Hoffmann, M Lis, F Hijaz, A Agarwal, S Devadas 2011 IEEE 29th International Conference on Computer Design (ICCD), 411-418, 2011 | 11 | 2011 |
| Reuse Aware Cache Line Insertion And Victim Selection In Large Cache Memory F Hijaz, G Patsilaras US Patent App. 15/695,732, 2019 | 9 | 2019 |
| Rethinking Last-Level Cache Management for Multicores Operating at Near-Threshold Voltages F Hijaz, O Khan Second Workshop on Near-threshold Computing, 2014 | 9 | 2014 |
| Performance by retaining high locality data in higher level cache memory F Hijaz, G Patsilaras US Patent 10,503,656, 2019 | 8 | 2019 |
| Locality-aware data replication in the last-level cache for large scale multicores F Hijaz, Q Shi, G Kurian, S Devadas, O Khan The Journal of Supercomputing 72, 718-752, 2016 | 8 | 2016 |
| NUCA-L1: A non-uniform access latency level-1 cache architecture for multicores operating at near-threshold voltages F Hijaz, O Khan ACM Transactions on Architecture and Code Optimization (TACO) 11 (3), 1-28, 2014 | 8 | 2014 |
| Towards efficient dynamic data placement in NoC-based multicores Q Shi, F Hijaz, O Khan 2013 IEEE 31st International Conference on Computer Design (ICCD), 369-376, 2013 | 8 | 2013 |
| Input/output-coherent Look-ahead Cache Access F Hijaz, AE Turner, B Rychlik US Patent App. 15/645,294, 2018 | 7 | 2018 |
| Exploring the performance implications of memory safety primitives in many-core processors executing multi-threaded workloads M Ahmad, SK Haider, F Hijaz, M van Dijk, O Khan Proceedings of the Fourth Workshop on Hardware and Architectural Support for …, 2015 | 6 | 2015 |
| Reducing Clean Evictions In An Exclusive Cache Memory Hierarchy F Hijaz US Patent App. 15/709,960, 2019 | 5 | 2019 |
| LDAC: Locality-aware data access control for large-scale multicore cache hierarchies Q Shi, G Kurian, F Hijaz, S Devadas, O Khan ACM Transactions on Architecture and Code Optimization (TACO) 13 (4), 1-28, 2016 | 5 | 2016 |
| Low-latency mechanisms for near-threshold operation of private caches in shared memory multicores F Hijaz, Q Shi, O Khan 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture …, 2012 | 4 | 2012 |
| M-map: Multi-factor memory authentication for secure embedded processors SK Haider, M Ahmad, F Hijaz, A Patni, E Johnson, M Seita, O Khan, ... 2015 33rd IEEE International Conference on Computer Design (ICCD), 471-474, 2015 | 2 | 2015 |
| Accelerating Communication in Single-chip Shared Memory Many-core Processors F Hijaz, B Kahne, P Wilson, O Khan Sixth Annual Boston Area Architecture Workshop, 2015 | 2 | 2015 |
| Performance By Retaining High Locality Data In Higher Level Cache Memory F Hijaz, G Patsilaras US Patent App. 16/565,882, 2020 | | 2020 |
