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Schuyler Eldridge
Schuyler Eldridge
Senior Staff Engineer at SiFive
Verified email at sifive.com - Homepage
Title
Cited by
Cited by
Year
Neural network-based accelerators for transcendental function approximation
S Eldridge, F Raudies, D Zou, A Joshi
Proceedings of the 24th edition of the great lakes symposium on VLSI, 169-174, 2014
352014
Resilient low voltage accelerators for high energy efficiency
N Chandramoorthy, K Swaminathan, M Cochet, A Paidimarri, S Eldridge, ...
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
322019
Towards General-Purpose Neural Network Computing
S Eldridge, J Appavoo, A Joshi, A Waterland, M Seltzer
Proceedings of the 2015 International Conference on Parallel Architecture …, 2015
282015
{PHMon}: A Programmable Hardware Monitor and Its Security Use Cases
L Delshadtehrani, S Canakci, B Zhou, S Eldridge, A Joshi, M Egele
29th USENIX Security Symposium (USENIX Security 20), 807-824, 2020
222020
Dyhard-dnn: Even more dnn acceleration with dynamic hardware reconfiguration
M Putic, S Venkataramani, S Eldridge, A Buyuktosunoglu, P Bose, M Stan
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
192018
Nile: A Programmable Monitoring Coprocessor
L Delshadtehrani, S Eldridge, S Canakci, M Egele, A Joshi
IEEE Computer Architecture Letters, 2017
132017
Digest generation
V Gopal, JD Guilford, S Eldridge, GM Wolrich, E Ozturk, WK Feghali
US Patent 9,292,548, 2016
122016
Learning to navigate in a virtual world using optic flow and stereo disparity signals
F Raudies, S Eldridge, A Joshi, M Versace
Artificial Life and Robotics 19 (2), 157-169, 2014
112014
Very low voltage (VLV) design
R Bertran, P Bose, D Brooks, J Burns, A Buyuktosunoglu, ...
2017 IEEE International Conference on Computer Design (ICCD), 601-604, 2017
102017
Chiffre: A Configurable Hardware Fault Injection Framework for RISC-V Systems
S Eldridge, A Buyuktosunoglu, P Bose
Second Workshop on Computer Architecture Research with RISC-V, 2018
72018
Determination and correction of physical circuit event related errors of a hardware design
P Bose, A Buyuktosunoglu, S Eldridge, KV Swaminathan, Y Zu
US Patent 10,365,327, 2019
62019
Self-evaluating array of memory
A Buyuktosunoglu, S Venkataramani, R Joshi, KV Swaminathan, ...
US Patent 10,607,715, 2020
52020
MLIR as hardware compiler infrastructure
S Eldridge, P Barua, A Chapyzhenka, A Izraelevitz, J Koenig, C Lattner, ...
Workshop on Open-Source EDA Technology (WOSET), 2021
32021
A Low Voltage RISC-V Heterogeneous System
S Eldridge, K Swaminathan, N Chandramoorthy, A Buyuktosunoglu, ...
First Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017
32017
Neural Network Computing Using On-Chip Accelerators
S Eldridge
Boston University, 2016
22016
A Programmable Hardware Monitor for Security of RISC-V Processors
L Delshadtehrani, S Canakci, B Zhou, S Eldridge, A Joshi, M Egele
Boston Area Architecture Workshop (BARC), 2020
12020
Varanus: An Infrastructure for Programmable Hardware Monitoring Units
L Delshadtehrani, J Appavoo, M Egele, A Joshi, S Eldridge
Boston Area Architecture Conference (BARC), 2017
12017
Exploiting hidden layer modular redundancy for fault-tolerance in neural network accelerators
S Eldridge, A Joshi
Proc. Boston area ARChitecture (BARC) Workshop, 2015
12015
Determination and correction of physical circuit event related errors of a hardware design
P Bose, A Buyuktosunoglu, S Eldridge, KV Swaminathan, Y Zu
US Patent App. 17/192,164, 2021
2021
Self-evaluating array of memory
A Buyuktosunoglu, S Venkataramani, R Joshi, KV Swaminathan, ...
US Patent 11,037,650, 2021
2021
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